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Course Module Information
Course Modules
EE451: System on Chip Design I
Semester 1 | Credits: 5
• CMOS circuits, mask set, fabrication steps (for small-scale circuit functions), simulation, reverse-engineering mask set
• Transmission gate-based circuit design
• nMOS/pMOS transistor I-V and transfer characteristics for varying transistor structural and fabrication parameters (level 1)
• 32-bit pipelined RV32I RISC-V processor architecture
• Operation of each RISC-V component and signal, for each instruction execution
• Creation, execution and debug of modular assembly language programs/functions using RISC-V instruction set, on simulators and processor hardware
• Processor HDL model creation, simulation and synthesis
• Extending processor architecture to support new instructions
• Processor pipelining, detection and handling
• C program to RISC-V assembly compilation
(Language of instruction: English)
Learning Outcomes
- Create CMOS circuits, mask set and fabrication steps, for small-scale CMOS circuit functions. Simulation. Reverse-engineering mask set.
- Analyse CMOS nMOS/pMOS transistor I-V and transfer characteristics for varying transistor structural and fabrication parameters (level 1)
- Describe and design 32-bit RV32I RISC-V processor architecture components which support execution of each instruction
- Create, execute and debug modular assembly language programs/functions using RISC-V instruction set, on simulators and on processor hardware
- Develop RV32I RISC-V processor HDL model, simulate and synthesise, modifying processor architecture to support new instructions
- Describe processor pipelining, detection and handling
- Explain and develop C programs for execution on RISC-V and their compilation to RISC-V assembly
Assessments
- Written Assessment (40%)
- Continuous Assessment (60%)
Teachers
- FEARGHAL MORGAN:
Research Profile |
Email
Note: Module offerings and details may be subject to change.